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Digi NS9750B-A1-C200
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Digi NS9750-A1 NET+ARM Processor, 352 pin RoHS BGA Package, Commercial temp, 200 MHz; Tray Quantity: 24   Minimum Order: 120 (*MOQ May Apply)
ESP Price: $64.52
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Availability: Usually Ships in 24 Hours; However, Due To Shortages Contact Sales to Verify
Product Code: NS9750B-A1-C200

Description Technical Specs & Box Contents Drivers & Downloads
The Digi NS9750B-A1 is a single chip 0.13μm CMOS network-attached processor. The CPU is the ARM926EJ-S core with MMU, DSP extensions, Jazelle Java accelerator, and 8 kB of instruction cache and 4 kB of data cache in a Harvard architecture. The NS9750B-A1 runs up to 200 MHz, with a 100 MHz system and memory bus and 50 MHz peripheral bus. The NS9750B-A1 operates at a 1.5V core and 3.3V I/O ring voltages.

With its extensive set of I/O interfaces, Ethernet high-speed performance and processing capacity, the NS9750B-A1 is the most capable of highly integrated 32-bit network-attached processors available. The NS9750B-A1 is designed specifically for use in high-performance intelligent networked devices and Internet appliances including highperformance/low-latency remote I/O, intelligent networked information displays, and streaming and surveillance cameras. The NS9750B-A1 is a member of the award-winning NET+ARM family of system-on-chip (SOC) solutions for embedded systems
32-bit ARM926EJ-S RISC processor
  • 125 to 200 MHz
  • 5-stage pipeline with interlocking
  • Harvard architecture
  • 8 kB instruction cache and 4 kB data cache
  • 32-bit ARM and 16-bit Thumb instruction sets. Can be mixed for performance/code density tradeoffs
  • MMU to support virtual memory-based OSs such as Linux, WinCE/Pocket PC, VxWorks, others „
  • DSP instruction extensions, improved divide, single cycle MAC
  • ARM Jazelle, 1200CM (coffee marks) Java accelerator EmbeddedICE-RT debug unit
  • JTAG boundary scan, BSDL support
External system bus interface
  • 32-bit data, 32-bit internal address bus, 28-bit external address bus
  • Glueless interface toSDRAM, SRAM, EEPROM, buffered DIMM, Flash
  • 4 static and 4 dynamic memory chip selects
  • 1-32 wait states per chip select A shared Static Extended Wait register allows transfers to have up to 16368 wait states that can be externally terminated.
  • Self-refresh during system sleep mode
  • Automatic dynamic bus sizing to 8 bits, 16 bits, 32 bits
  • Burst mode support with automatic data width adjustment
  • Two external DMA channels for external peripheral support System Boot
  • High-speed boot from 8-bit, 16-bit, or 32-bit ROM or Flash
  • Hardware-supported low cost boot from serial EEPROM through SPI port (patent pending)
High performance 10/100 Ethernet MAC
  • 10/100 Mbps MII/RMII PHY interfaces
  • Full-duplex or half-duplex
  • Station, broadcast, or multicast address filtering
  • 2 kB RX FIFO
  • 256 byte TX FIFO with on-chip buffer descriptor ring – Eliminates underruns and decreases bus traffic
  • Separate TX and RX DMA channels
  • Intelligent receive-side buffer size selection
  • Full statistics gathering support
  • External CAM filtering support
PCI/CardBus port
  • PCI v2.2, 32-bit bus, up to 33 MHz bus speed Programmable to: – PCI device mode – PCI host mode: Supports up to 3 external PCI devices Embedded PCI arbiter or external arbiter
  • CardBus host mode

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